The limits of planar transistors have constrained efforts to increase integrated circuit performance while decreasing the size of devices. Recently developed fin-based transistors enable denser packing of device components and greater current control with the use of wrap-around dual- and tri-gates. Use of multiple fins enables further tailoring of device specifications and increased performance. However, source/drain contacts for multi-fin devices are typically formed over the top edges of the fins, which can lead to high resistance due to current crowding at the fin tips.